Structure for dynamically allocating lanes to a plurality of PCI express connectors
US8103993B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 2, 2008 |
| Grant date | Jan 24, 2012 |
| Priority date | — |
| Expiry date | Mar 21, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4022
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for dynamically allocating lanes to a plurality of PCI Express connectors is disclosed that include identifying whether a PCI Express device is installed into each PCI Express connector, and assigning a portion of the lanes to each PCI Express connector having a PCI Express device installed into the PCI Express connector. Dynamically allocating lanes to a plurality of PCI Express connectors may also include identifying a device type for each PCI Express device installed into the plurality of PCI Express connectors, creating allocation rules that specify the allocation of lanes to the plurality of PCI Express connectors, and receiving user allocation preferences that specify the allocation of lanes to the plurality of PCI Express connectors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.