Verifying non-deterministic behavior of a design under test
US8103998B2 · kind B2 · utility
1Cited by
7References
18Claims
0Family size
Assignee
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Key dates
| Filing date | Feb 20, 2008 |
| Grant date | Jan 24, 2012 |
| Priority date | — |
| Expiry date | May 22, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention generally relates to design verification, and more particularly to verification of non-deterministic behavior of a design under test. A method includes predicting a plurality of behaviors of a design under test (DUT), and forking respective verification tasks for each one of the plurality of behaviors. The method further includes verifying an actual behavior of the DUT with each of the verification tasks, and terminating a respective one of the verification tasks when the actual behavior of the DUT does not conform to the respective one of the verification tasks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.