Layout design apparatus, layout design method, and computer product
US8104008B2 · kind B2 · utility
1Cited by
5References
12Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 22, 2008 |
| Grant date | Jan 24, 2012 |
| Priority date | — |
| Expiry date | Dec 14, 2029 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A layout design apparatus that limits the maximum wiring density and the maximum edge length of partial regions when determining wiring layout. After determining the wiring layout, the layout design apparatus inserts a dummy into a partial region having a low wiring density and thereby, the minimum wiring density and the minimum edge length of the partial regions are limited. Thus, the respective wiring densities and respective edge lengths of the partial regions are constrained within a constant range and irregularities in the substrate surface after polishing can be suppressed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.