Semiconductor integrated circuit design supporting method, semiconductor integrated circuit design supporting system, and computer readable medium
US8104010B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 6, 2008 |
| Grant date | Jan 24, 2012 |
| Priority date | — |
| Expiry date | Apr 12, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2113/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor integrated circuit design supporting system has a memory unit which stores cell information containing the number of power supply pads formed at a chip as well as names and the number of a plurality of IO cells, and a drive factor definition file defining a drive factor of each of the plurality of IO cells, a pad laying out section which tentatively lays out the power supply pads and input-output pads corresponding to the IO cells, using the cell information, a package virtual designing section which prepares a package drawing based on coordinates of the power supply pads and the input-output pads, which have been tentatively laid out, an electric characteristics data calculating section which calculates inductance of the power supply pads, using the package drawing, and a noise risk calculating section which calculates noise risk of each of the input-output pads, using the inductance and the drive factor definition file.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.