Power-on-reset circuit with brown-out reset for multiple power supplies
US8106688B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 18, 2009 |
| Grant date | Jan 31, 2012 |
| Priority date | — |
| Expiry date | Sep 28, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/24
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A power-on reset circuit includes a first circuit and a second circuit. The first circuit include a first NMOS transistor having a gate controlled by a low voltage supply VDD_L, a resistor connected between the source of the first NMOS transistor and a voltage supply VSS that is lower than VDD_L, and one or more diodes serially connected between a high voltage supply VDD_H and the drain of the first NMOS transistor. The second circuit includes a first PMOS transistor having a source connected to VDD_L, a second PMOS transistor having a source connected to the drain of first PMOS transistor, a second NMOS transistor connected between the drain of the second PMOS transistor and VSS, and an inverter configured to output a signal in response to the power on of the high voltage supply VDD_H and the low voltage supply VDD_L.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.