High signal level compliant input/output circuits
US8106699B2 · kind B2 · utility
3Cited by
47References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 29, 2008 |
| Grant date | Jan 31, 2012 |
| Priority date | — |
| Expiry date | Jul 29, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018507
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A level shifter has at least one of either a pull up or a pull down circuit. The circuit is made of electronic components with reliability limits less than a maximum signal level output by the level shifter. The level shifter also has a timing circuit coupled to at least on of either the pull up or pull down circuit. The timing circuit controls a time of application of an input signal to at least one of either the pull up or pull down circuit preventing a terminal to terminal signal level experienced by the electronic components exceeding the reliability limits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.