DC biasing circuit for a metal oxide semiconductor transistor
US8106706B2 · kind B2 · utility
9Cited by
3References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 9, 2009 |
| Grant date | Jan 31, 2012 |
| Priority date | — |
| Expiry date | Sep 4, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F1/301
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A method for biasing a MOS transistor includes AC coupling an input signal from an amplifier stage to a gate of the MOS transistor. The method includes connecting a pair of diodes in an opposing parallel configuration to a bias transistor and a current source. Further, the method includes generating a DC bias voltage through the bias transistor and the current source. The method also includes clamping the voltage at drain of the bias transistor to a fixed voltage by a clamping circuit. Further, the method includes coupling the DC bias voltage to the gate of the MOS transistor through the pair of diodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.