Burst processing modem
US8107515B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 17, 2009 |
| Grant date | Jan 31, 2012 |
| Priority date | — |
| Expiry date | Sep 1, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0045
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A burst processing modem. Implementations may include a receive side including a channelizer adapted to process a plurality of channels and write a plurality of frames to a receive RAM array. A receive frame state machine may be adapted to generate a timing signal using a burst time plan for the plurality of frames. A demodulator may be coupled with the receive RAM array and adapted to read from the receive RAM array only the one or more bursts from the plurality of frames indicated by the timing signal. A transmit side may include a modulator coupled with a transmit frame state machine, with a transmit RAM array, and a combiner bank. The combiner bank may read the modulated plurality of channels from the transmit RAM array and assemble a plurality of frames using a timing signal generated from a burst time plan by the transmit frame state machine.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.