Digital logic circuit, shift register and active matrix device
US8107587B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 27, 2009 |
| Grant date | Jan 31, 2012 |
| Priority date | — |
| Expiry date | Mar 27, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2310/0286
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital logic circuit includes a plurality of transistors of a same conduction type. In at least one embodiment, a first transistor has a source, gate and drain connected to a first circuit node, a second circuit node and a first power supply line, respectively. A second transistor has a source, gate and drain connected to the second node, the first node and the first supply line, respectively. A third transistor has a drain connected to the first node. A fourth transistor has a gate and drain connected to a third circuit node and the second circuit node, respectively. A fifth transistor has a gate and drain connected to the first and third nodes, respectively. Such a circuit may be used, for example, as a latch in a shift register of an active matrix addressing arrangement.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.