Patent · US Active

Method to verify an implemented coherency algorithm of a multi processor environment

US8108197B2 · kind B2 · utility

7Cited by

2References

15Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Christian Habermann · Stuttgart, DE
Ralf Winkelmann · Eppelheim, DE
Hans-Werner Tast · Holzgerlingen, DE
Christian Jacobi · West Park, US

Key dates

Filing date	Dec 4, 2008
Grant date	Jan 31, 2012
Priority date	—
Expiry date	Jan 15, 2030

Classification

Technology area (CPC G)Physics
CPC primaryG06F12/0815
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A coherency algorithm for a multi processor environment to run on a single processor model is verified by: generating a reference model reflecting a private cache hierarchy of a single processor within the multi processor environment, stimulating the private cache hierarchy with simulated requests and/or cross invalidations from a core side and/or from a nest side, and augmenting all data available in the private cache hierarchy with two construction dates and two expiration dates, which are set based on interface events. Multi processor coherency is not observed if the cache hierarchy ever returns data to the processor with an expiration date that is older than the latest construction date of all data used before. Further, a single processor model and a computer program product can be employed to execute the method.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.