Processor architectures for enhanced computational capability and low latency
US8108653B2 · kind B2 · utility
7Cited by
3References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 5, 2010 |
| Grant date | Jan 31, 2012 |
| Priority date | — |
| Expiry date | Feb 5, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/8015
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor includes a compute array comprising a first plurality of compute engines serially connected along a data flow path such that data flows between successive compute engines at successive times. The first plurality of compute engines includes an initial compute engine and a final compute engine. The data flow path includes a recirculation path connecting the final compute engine to the initial compute engine with no compute engine therebetween.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.