Handling floating point operations
US8108657B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 28, 2008 |
| Grant date | Jan 31, 2012 |
| Priority date | — |
| Expiry date | Mar 13, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computing system capable of handling floating point operations during program code conversion is described, comprising a processor including a floating point unit and an integer unit. The computing system further comprises a translator unit arranged to receive subject code instructions including at least one instruction relating to a floating point operation and in response to generate corresponding target code for execution on said processor. To handle floating point operations a floating point status unit and a floating point control unit are provided within the translator. These units are cause the translator unit to generate either: target code for performing the floating point operations directly on the floating point unit; or target code for performing the floating point operations indirectly, for example using a combination of the integer unit and the floating point unit. In this way the efficiency of the computing system is improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.