Programmable logic device programming verification systems and methods
US8108754B1 · kind B1 · utility
2Cited by
5References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 24, 2010 |
| Grant date | Jan 31, 2012 |
| Priority date | — |
| Expiry date | Sep 21, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/09
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a method of verifying a programming operation of a programmable logic device includes storing in non-volatile memory within the programmable logic device configuration data and a pre-calculated code value based on the configuration data. The method further includes transferring the configuration data from non-volatile memory to configuration memory within the programmable logic device; calculating a code value based on the configuration data transferred from the non-volatile memory to the configuration memory; and comparing the calculated code value to the pre-calculated code value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.