Method for incorporating existing silicon die into 3D integrated stack
US8110899B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2006 |
| Grant date | Feb 7, 2012 |
| Priority date | — |
| Expiry date | Dec 4, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An apparatus including a first die including a plurality of conductive through substrate vias (TSVs); and a plurality of second dice each including a plurality of contact points coupled to the TSVs of the first die, the plurality of second dice arranged to collectively include a surface area approximating a surface area of the first die. A method including arranging a plurality of second dice on a first die such that collectively the plurality of second dice include a surface area approximating the surface area of the first die; and electrically coupling a plurality of second device to a plurality of the first die. A system including an electronic appliance including a printed circuit board and a module, the module including a first die including a plurality of TSVs; and the plurality of second dice arranged to collectively include a surface area approximating the surface area of the first die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.