Patent · US Active

Register with process, supply voltage and temperature variation independent propagation delay path

US8111092B2 · kind B2 · utility

2Cited by
3References
10Claims
0Family size

Assignee

Inventors

Key dates

Filing dateMay 29, 2008
Grant dateFeb 7, 2012
Priority date
Expiry dateDec 8, 2030

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG11C29/028
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

A digital data register is disclosed that provides setup and hold timing on the pre-register side, clock centering on the post-register side, and constant propagation delay time over variations in process, supply voltage and temperature (PVT) using a novel means to generate and distribute the clock signal. These features allow the register to be used in applications operating at clock frequencies in excess of 800 MHz.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.