Setting controller termination in a memory controller and memory device interface in a communication bus
US8111564B2 · kind B2 · utility
3Cited by
17References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 29, 2009 |
| Grant date | Feb 7, 2012 |
| Priority date | — |
| Expiry date | Dec 27, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4086
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A DRAM and memory controller are coupled during driver training to reduce mismatches. The impedances of the system are controlled through a termination at the controller to yield improvements in timing margins. The coupling of the components on a shared electrical bus through adjustment of the termination values during training removes known offset issues.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.