3D optoelectronic packaging
US8111730B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 20, 2009 |
| Grant date | Feb 7, 2012 |
| Priority date | — |
| Expiry date | Nov 7, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/806
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
An optoelectronic (OE) package or system and method for fabrication is disclosed which includes a silicon layer with a wiring layer. The silicon layer has an optical via for allowing light to pass therethrough. An optical coupling layer is bonded to the silicon layer, and the optical coupling layer includes a plurality of microlenses for focusing and or collimating the light through the optical via. One or more first OE elements are coupled to the silicon layer and electrically communicating with the wiring. At least one of the first OE elements positioned in optical alignment with the optical via for receiving the light. A second OE element embedded within the wiring layer. A carrier may be interposed between electrical interconnect elements and positioned between the wiring layer and a circuit board.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.