Time-domain equalizer
US8111740B2 · kind B2 · utility
0Cited by
2References
9Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 29, 2006 |
| Grant date | Feb 7, 2012 |
| Priority date | — |
| Expiry date | Jan 24, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/03133
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The present invention provides a cost-effective TEQ hardware architecture to support multiple VDSL2 profiles. It supports variable TEQ tap length programmable through firmware. Larger TEQ tap length at low-speed profiles is supported by the unique design without adding additional multipliers. The maximum number of TEQ taps supported is actually inversely proportional to the profile frequency. This perfectly meets the requirement to have longer TEQ for low-speed profile and shorter TEQ for high-speed profile.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.