Controlling complex non-linear data transfers
US8112560B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 24, 2010 |
| Grant date | Feb 7, 2012 |
| Priority date | — |
| Expiry date | Aug 24, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A direct memory access controller for controlling data transfer between a plurality of data sources and a plurality of data destinations is disclosed. The plurality of data sources and data destinations communicate with the direct memory access controller via a plurality of channels, the direct memory access controller further communicates with a memory and a processor. The memory stores two sets of control data for each of the plurality of channels and for the processor. The direct memory access controller is responsive to a data transfer request received from one of said plurality of channels or from said processor to access one set of said corresponding control data stored in said memory, said direct memory access performing at least a portion of said data transfer requested in dependence upon said accessed control data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.