Methods and apparatus for reducing command processing latency while maintaining coherence
US8112590B2 · kind B2 · utility
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22Claims
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Key dates
| Filing date | Aug 29, 2007 |
| Grant date | Feb 7, 2012 |
| Priority date | — |
| Expiry date | Sep 7, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0831
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a first aspect, a first method of reducing command processing latency while maintaining memory coherence is provided. The first method includes the steps of (1) providing a memory map including memory addresses available to a system; and (2) arranging the memory addresses into a plurality of groups. At least one of the groups does not require the system, in response to a command that requires access to a memory address in the group from a bus unit, to get permission from all remaining bus units included in the system to maintain memory coherence. Numerous other aspects are provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.