Single cycle reduced complexity CPU
US8112615B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 27, 2002 |
| Grant date | Feb 7, 2012 |
| Priority date | — |
| Expiry date | Oct 25, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3004
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A single cycle RISC CPU. The single cycle RISC CPU includes an instruction decoder configured to perform an instruction fetch and an instruction decode. An arithmetic logic unit is coupled to the instruction decoder. The arithmetic logic unit is configured to perform an instruction execute and produce a resulting data output. A register file is coupled to the arithmetic logic unit. The register file includes a register input and a register output. The register file is configured to provide data for the instruction fetch via the register output and accept the resulting data output via the register input such that the instruction fetch, the instruction decode, and the instruction execute are performed in a single clock cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.