Data-mover controller with plural registers for supporting ciphering operations
US8112635B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 9, 2009 |
| Grant date | Feb 7, 2012 |
| Priority date | — |
| Expiry date | Mar 10, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04W12/033
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A data processing system ciphers and transfers data between a first memory unit and a second memory unit, such as, for example, between a share memory architecture (SMA) static random access memory (SRAM) and a double data rate (DDR) synchronous dynamic random access memory (SDRAM). The system includes a ciphering engine and a data-mover controller. The data-mover controller includes at least one register having a field that specifies whether or not the transferred data should be ciphered. If the field specifies that the transferred data should be ciphered, the field also specifies the type of ciphering that is to be performed, such as a third generation partnership project (3GPP) standardized confidentially cipher algorithm “f8” or integrity cipher algorithm “f9”.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.