Method and system for controlling power in a chip through a power-performance monitor and control unit
US8112642B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 3, 2008 |
| Grant date | Feb 7, 2012 |
| Priority date | — |
| Expiry date | Sep 25, 2029 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for controlling power and performance in a microprocessor system includes a monitoring and control system integrated into a microprocessor system. The monitoring and control system includes a hierarchical architecture having a plurality of layers. Each layer in the hierarchal architecture is responsive to commands from a higher level, and the commands provide instructions on operations and power distribution, such that the higher levels provide modes of operation and budgets to lower levels and the lower levels provide feedback to the higher levels to control and manage power usage in the microprocessor system both globally and locally.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.