Patent · US Active

Clock distribution chip

US8112656B1 · kind B1 · utility

0Cited by

2References

12Claims

0Family size

Assignee

Lattice Semiconductor Corporation · US

Inventors

Shyam Chandra · Portland, US
Om P. Agrawal · Los Altos, US
Ludmil Nikolov · Cupertino, US
Harald Weller · Southampton, GB
Douglas C. Morse · Yamhill, US

Key dates

Filing date	Oct 13, 2009
Grant date	Feb 7, 2012
Priority date	—
Expiry date	Aug 14, 2030

Classification

Technology area (CPC G)Physics
CPC primaryG06F1/10
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

In one embodiment, a clock distribution chip includes a first clock input adapted to receive a first single-ended input clock signal, a second clock input adapted to receive a second single-ended input clock signal, and input buffer circuitry coupled to the first and second clock inputs. The input buffer circuitry is adapted to select an input clock signal among the first single-ended input clock signal, the second single-ended input clock signal, and a differential input clock signal derived from the first and second single-ended input clock signals. A phase-locked loop (PLL) is adapted to receive an input clock signal selected by the input buffer circuitry and to generate a PLL clock signal based on the selected input clock signal. A clock output provides an output clock signal based on the PLL clock signal.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.