Disposable spacer integration with stress memorization technique and silicon-germanium

US8114727B2 · kind B2 · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventors

• Weize Xiong · Austin, US
• Zhiqiang Wu · Plano, US
• Xin Wang · Chandler, US

Key dates

• Filing date: Aug 28, 2009
• Grant date: Feb 14, 2012
• Expiry date: Aug 28, 2029

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/017

Abstract

An integrated process flow for forming an NMOS transistor (104) and an embedded SiGe (eSiGe) PMOS transistor (102) using a stress memorization technique (SMT) layer (126). The SMT layer (126) is deposited over both the NMOS transistor (104) and PMOS transistor (102). The portion of SMT layer (126) over PMOS transistor (102) is anisotropically etched to form spacers (128) without etching the portion of SMT layer (126) over NMOS transistor (104). Spacers (128) are used to align the SiGe recess etch and growth to form SiGe source/drain regions (132). The source/drain anneals are performed after etching the SMT layer (126) such that SMT layer (126) provides the desired stress to the NMOS transistor (104) without degrading PMOS transistor (102).