Laminated stress overlayer using In-situ multiple plasma treatments for transistor improvement
US8114784B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 14, 2010 |
| Grant date | Feb 14, 2012 |
| Priority date | — |
| Expiry date | Oct 14, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Integrated circuits (ICs) commonly contain pre-metal dielectric (PMD) liners with compressive stress to increase electron and hole mobilities in MOS transistors. The increase is limited by the thickness of the PMD liner. The instant invention is a multi-layered PMD liner in an integrated circuit which has a higher stress than single layer PMD liners. Each layer in the inventive PMD liner is exposed to a nitrogen-containing plasma, and which has a compressive stress higher than 1300 MPa. The PMD liner of the instant invention is composed of 3 to 10 layers. The hydrogen content of the first layer may be increased to improve transistor properties such as flicker noise and Negative Bias Temperature Instability (NBTI). An IC containing the inventive PMD liner and a method for forming same are also claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.