Integrated circuit for reducing nonlinearity in sampling networks
US8115518B1 · kind B1 · utility
12Cited by
10References
15Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 16, 2010 |
| Grant date | Feb 14, 2012 |
| Priority date | — |
| Expiry date | Aug 16, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0054
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit allows for the correction of distortion at an input of a sampling network. The integrated circuit contains a first bootstrap circuit to drive a sampling network transistor and a second bootstrap circuit to separate the back-gate terminal of the transistor from a voltage input by a resistance inserted in series. The presence of the inserted resistance counteracts the effect of the nonlinear back-gate capacitance on the distortion at the input.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.