Device and control method of device
US8115529B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 25, 2009 |
| Grant date | Feb 14, 2012 |
| Priority date | — |
| Expiry date | Oct 27, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0812
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A frequency divider section generates a frequency-divided clock RSELO by dividing the frequency of an internal clock LCLK, which lags behind an external clock in phase, and generates a delayed frequency-divided clock RSELI by delaying the frequency-divided clock RSELO. A signal input from the outside in synchronization with an internal clock PCLK which lags behind the external clock in phase is held in a latch circuit in synchronization with the delayed frequency-divided clock RSELI. Then, an output signal of the latch circuit is read into a latch circuit in synchronization with the frequency-divided clock RSELO and is output as a signal which is synchronized with the internal clock LCLK. In addition, a frequency divider section includes a variable divider which divides the frequency of the internal clock LCLK by a predetermined divide ratio which can be changed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.