Leakage current suppressing circuit and semiconductor chip
US8115535B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 16, 2009 |
| Grant date | Feb 14, 2012 |
| Priority date | — |
| Expiry date | Apr 16, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0016
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A leakage current suppressing circuit includes a bias generating unit and a switch unit. The bias generating unit is adapted to be coupled to a power source and an output terminal, and generates a bias voltage substantially equal to a voltage at the power source when the power source is turned on, and substantially equal to a voltage at the output terminal when the power source is turned off. The switch unit includes a first P-type transistor having a first terminal adapted to be coupled to the power source, a second terminal adapted to be coupled to the output terminal, a gate terminal, and a body terminal coupled to the bias generating unit for receiving the bias voltage therefrom.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.