ESD protection for differential output pairs
US8116048B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 12, 2009 |
| Grant date | Feb 14, 2012 |
| Priority date | — |
| Expiry date | Jun 27, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02H3/22
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
In a conventional differential output circuit, the output terminals are connected to the drains of a differential pair of transistors and the sources of the transistors are connected together at a first node. The bodies of the transistors are connected to a second node having a potential different from that of the first node. In the event of a HBM ESD event, discharge may take place through the differential transistors, leading to destruction of one of them. To reduce the likelihood of such discharge, in a preferred embodiment, switches are provided to connect the body of each of the differential transistors to the first node when an ESD event is sensed. In an alternative embodiment, a switch is provided to connect the first node to the second node when an ESD event is sensed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.