Method and apparatus for SerDes jitter tolerance improvement
US8116409B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 28, 2009 |
| Grant date | Feb 14, 2012 |
| Priority date | — |
| Expiry date | Aug 5, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0337
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Apparatus and methods detect the presence of an isolated pulse in a communications signal, such as a data signal carrying data for a serializer/deserializer (SerDes). An example of an isolated pulse is a “1” pulse preceded and followed by “0” pulses, or a “0” pulse preceded and followed by a “1” pulse. These isolated pulses can exhibit a narrow pulse width, and under severe jitter conditions, may not align with a baud sample point, which can cause the isolated pulse to be missed, resulting in a data decoding error. By detecting the presence of these isolated pulses and determining the most likely baud period to which they belong, jitter tolerance can be improved for many channel conditions. This can improve jitter tolerance of a SerDes receiver for links that suffer from various sources of Deterministic Jitter (DJ) such as Duty Cycle Distortion (DCD) and Inter-Symbol Interference (ISI).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.