Reducing common mode effects in an output stage
US8116700B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 16, 2009 |
| Grant date | Feb 14, 2012 |
| Priority date | — |
| Expiry date | Aug 9, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B1/0458
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a power amplifier may include an output stage with multiple transformers and corresponding matching capacitances. The capacitances may include a first matching capacitance coupled in parallel with a secondary coil of a first transformer and a second matching capacitance coupled in parallel with a secondary coil of a second transformer, where the secondary coils are coupled in series in an output stack configuration. By accounting for parasitics present in the power amplifier, the first matching capacitance can be designed to have a greater capacitance than the second matching capacitor, even where the first and second transformers are configured to output substantially equal power levels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.