VDSL2 transmitter/receiver architecture
US8117250B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 29, 2006 |
| Grant date | Feb 14, 2012 |
| Priority date | — |
| Expiry date | Jun 15, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/265
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The invention suggests a novel pipeline FFT/IFFT architecture that not only produces time-domain samples (after IFFT) but also pushes time-domain samples into FFT in a time-based sequential order. This reduces external memory requirement for buffering the time-domain samples. Also the design is based on a mixed radix-2 and radix-22 algorithm aiming at reducing number of multipliers and adders. Compared with other FFT/IFFT design methodologies such as radix-4, it achieves the minimum multiplier use, the minimum adder use and the minimum operating memory use. On the other hand, the design architecture not only can support different FFT/IFFT size required by different VDSL2 profiles but also utilizing a novel pipeline control mechanism to reduce logic switching at low-speed profiles. This effectively further reduces the power consumption at lower profiles and enables our VDSL2 digital chipsets to compete with ADSL2+ systems in terms of power consumption.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.