Microprocessor memory management
US8117490B2 · kind B2 · utility
2Cited by
25References
16Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 30, 2006 |
| Grant date | Feb 14, 2012 |
| Priority date | — |
| Expiry date | Apr 22, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0409
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory for an electronic brake control system is divided into portions that are classified as critical and non-critical. Each portion is periodically tested for faults. Upon detection of a fault, the memory is reconfigured with any operations of the brake system associated with a critical memory portion permanently disabled and any operations of the brake system associated with a non-critical memory portion temporarily disabled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.