Method for parallel data integrity checking of PCI express devices
US8117525B2 · kind B2 · utility
2Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 21, 2006 |
| Grant date | Feb 14, 2012 |
| Priority date | — |
| Expiry date | Aug 15, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2001/0094
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for supporting PCI Express is disclosed. A physical layer has a PCI Express interface for receiving data from a PCI Express compatible communication medium. The data is in the form of a packet. A data link layer is disclosed for verifying a CRC value and a sequence number received within the packet. A transaction layer is disclosed for receiving the packet from the data link layer and for processing thereof. The transaction layer processes at least some of the packet data in parallel to the data link layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.