Method of manufacturing semiconductor package and method of manufacturing substrate for the semiconductor package
US8119451B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 4, 2010 |
| Grant date | Feb 21, 2012 |
| Priority date | — |
| Expiry date | Sep 2, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10674
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a semiconductor package, includes the steps of: forming a substrate on which a semiconductor chip is to be mounted; and mounting the semiconductor chip on the substrate through connection bumps, the substrate forming step including a first step of forming a plurality of electrode pads to be bonded to the connection bumps on a part of a support plate, a second step of forming one or more wiring layers on the support plate including the electrode pads with an insulation layer interposed between them, thereby forming a substrate having the electrode pads formed thereon on one side thereof, and a third step of removing the substrate from the support plate, wherein a plurality of first convex portions are formed on the support plate prior to the first step, and the electrode pads are formed on the first convex portions at the first step.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.