Self-aligned process for nanotube/nanowire FETs
US8119466B2 · kind B2 · utility
499Cited by
3References
20Claims
0Family size
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Key dates
| Filing date | Jun 3, 2011 |
| Grant date | Feb 21, 2012 |
| Priority date | — |
| Expiry date | Jun 3, 2031 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S977/938
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A complementary metal oxide semiconductor (CMOS) device, e.g., a field effect transistor (FET), that includes at least one one-dimensional nanostructure that is typically a carbon-based nanomaterial, as the device channel, and a metal carbide contact that is self-aligned with the gate region of the device is described. The present invention also provides a method of fabricating such a CMOS device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.