Printed circuit board and semiconductor package
US8119918B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 1, 2006 |
| Grant date | Feb 21, 2012 |
| Priority date | — |
| Expiry date | May 15, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/09909
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An object of the present invention is to prevent occurrence of an electrical fault such as signal disconnection due to exfoliation between a via and a printed circuit board, via crack, or the like, caused by various stresses that may arise when the printed circuit board is curved. The printed circuit board includes a first wiring layer 11, an electrical insulating base material 12 formed on the first wiring layer 11 and including a via base hole 12a that leads to the first wiring layer 11, and a second wiring layer 16 that is formed on the electrical insulating base material 12 and is electrically connected to the first wiring layer 11 through the via base hole 12a. In a region of the second wiring layer 16 disposed at least in the vicinity of the via base hole 12a, a stress relieving portion 17 is formed which relieves bending stress, tensile stress, compressive stress, and shear stress that may arise when the electrical insulating base material 12 is curved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.