Tunnel field-effect transistor with gated tunnel barrier
US8120115B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Mar 7, 2008 |
| Grant date | Feb 21, 2012 |
| Priority date | — |
| Expiry date | Apr 2, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/123
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A tunnel field effect transistor (TFET) is disclosed. In one aspect, the transistor comprises a gate that does not align with a drain, and only overlap with the source extending at least up to the interface of the source-channel region and optionally overlaps with part of the channel. Due to the shorter gate, the total gate capacitance is reduced, which is directly reflected in an improved switching speed of the device. In addition to the advantage of an improved switching speed, the transistor also has a processing advantage (no alignment of the gate with the drain is necessary), as well as a performance improvement (the ambipolar behavior of the TFET is reduced).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.