Semiconductor device and method of forming the same
US8120123B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 1, 2010 |
| Grant date | Feb 21, 2012 |
| Priority date | — |
| Expiry date | Apr 1, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
Abstract
A semiconductor device, and a method of forming the same, includes forming a cell bit line pattern and a peripheral gate pattern on a semiconductor substrate. The cell bit line pattern may be formed on an inactive region adjacent to a cell active region of the semiconductor substrate. The peripheral gate pattern may be disposed on a peripheral active region of the semiconductor substrate. A cell contact plug may be formed between the cell bit line pattern and the cell active region. A peripheral contact plug may be formed on the peripheral active region on a side of the peripheral gate pattern. An insulating layer may be formed to expose top surfaces of the cell bit line pattern, the peripheral gate pattern, and the cell and peripheral contact plugs at substantially the same level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.