Protected semiconductor device and method of manufacturing thereof
US8120146B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 6, 2007 |
| Grant date | Feb 21, 2012 |
| Priority date | — |
| Expiry date | Dec 31, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19041
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The semiconductor device (100) comprises at least one semiconductor element (20), a metallization structure comprising a first (31) and a second line (32) and extending thereon a resistor. An electrically insulating protection layer (36) is present on the resistor (35) and is defined in a pattern that is substantially identical to the resistor pattern and has a temperature stability up to a temperature that is at least equal to a deposition temperature of a passivation layer (37) to be deposited thereon so as to cover the metallization structure. Both the resistor (35) and the protection layer (36) are deposited conformally on the metallization structure and any underlying substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.