Patent · US Active

Integrated circuit and method

US8120186B2 · kind B2 · utility

34Cited by

4References

21Claims

0Family size

Assignee

Qimonda AG · DE

Inventor

Kimyung Yoon · Dresden, DE

Key dates

Filing date	Feb 15, 2008
Grant date	Feb 21, 2012
Priority date	—
Expiry date	May 1, 2029

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/3511
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

An integrated circuit and method of fabricating an integrated circuit. One embodiment includes a circuit chip, a contact pad, and a projecting top contact. A signal line couples the contact pad to the projecting top contact, the contact pad, the projecting top contact. The signal line is arranged on a top face of the circuit chip. A substrate and a lower contact pad, the lower contact pad is arranged on a bottom face of the substrate and the circuit chip is arranged on a top face of the substrate. A bottom face of the circuit chip is facing the top face of the substrate. A connection couples the contact pad on the circuit chip to the lower contact pad.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.