Configurable low drop out regulator circuit
US8120390B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 19, 2009 |
| Grant date | Feb 21, 2012 |
| Priority date | — |
| Expiry date | May 27, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F1/56
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A low drop out voltage regulator (LDO) is capable of operating in one of two different modes based on externally connected components. In one mode, the LDO directly generates a regulated output voltage. In a second mode, the LDO drives an external PNP transistor to generate a regulated output voltage. In both modes, a relatively large bypass capacitor may be connected to the output voltage node to bypass high-frequency loading on the output voltage node. However, the bypass capacitor creates a low frequency pole in the frequency response of the LDO, which can diminish phase margin and reduce overall stability. An on chip compensation network beneficially counteracts the low frequency pole with an appropriately placed zero, thereby resulting in improved phase margin and greater stability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.