Method and apparatus for arranging multiple processors on a semiconductor chip
US8120938B2 · kind B2 · utility
4Cited by
3References
4Claims
0Family size
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Key dates
| Filing date | Apr 18, 2008 |
| Grant date | Feb 21, 2012 |
| Priority date | — |
| Expiry date | Dec 22, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/8023
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for connecting multiple cores to form a multi core processor. Each processor is connected to at least two other processors, each of which is a mirror image of the first processor. The processors are connected to form a two dimensional matrix connected by one drop busses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.