Multi-bank memory device method and apparatus
US8120985B2 · kind B2 · utility
4Cited by
6References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 12, 2008 |
| Grant date | Feb 21, 2012 |
| Priority date | — |
| Expiry date | Nov 15, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a memory device comprises a semiconductor substrate, a first set of memory banks disposed on the semiconductor substrate and a second set of memory banks disposed on the semiconductor substrate. Each memory bank of the second set is split into a plurality of memory bank segments physically separated from each other and from the first set of memory banks. Each memory bank segment is arranged adjacent to, and occupies less area than, one of the memory banks of the first set.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.