Unidirectional sweep training for an interconnect
US8121239B2 · kind B2 · utility
2Cited by
4References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 11, 2008 |
| Grant date | Feb 21, 2012 |
| Priority date | — |
| Expiry date | Dec 23, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0083
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
In one embodiment, the present invention includes a receiver having a delay lock loop (DLL) to receive a clock signal and to generate a plurality of clock phases therefrom, and an offset controller including a first register set for a first phase interpolator and a second register set for a second phase interpolator. At initiation of a track pre-tune process, both phase interpolators are controlled to generate sampling signals at a common clock phase. Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.