Method of controlling refresh operation in multi-port DRAM and a memory system using the method
US8122188B2 · kind B2 · utility
6Cited by
4References
12Claims
0Family size
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Key dates
| Filing date | Jul 25, 2006 |
| Grant date | Feb 21, 2012 |
| Priority date | — |
| Expiry date | Sep 2, 2027 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-port memory system includes a shared memory bank, and a refresh controller coupled to the shared memory bank, and configured to selectively apply refresh commands from multiple processors to the shared memory bank.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.