Multi port memory device with shared memory area using latch type memory cells and driving method
US8122199B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 25, 2009 |
| Grant date | Feb 21, 2012 |
| Priority date | — |
| Expiry date | Feb 28, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1075
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiport semiconductor memory device includes; first and second port units respectively coupled to first and second processors, first and second dedicated memory area accessed by first and second processors, respectively and implemented using DRAM cells, a shared memory area commonly accessed by the first and second processors via respective first and second port units and implemented using memory cells different from the DRAM cells implementing the first and second dedicated memory areas, and a port connection control unit controlling data path configuration between the shared memory area and the first and second port units to enable data communication between the first and second processors through the shared memory area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.