System and method for memory architecture configuration
US8122208B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 25, 2009 |
| Grant date | Feb 21, 2012 |
| Priority date | — |
| Expiry date | Mar 5, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0646
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods for reducing problems and disadvantages associated with physically asymmetrical memory structures are disclosed. A method for configuring memories in an information handling system having a plurality of memories, each memory local to one of a plurality of nodes, and wherein at least one memory of the plurality of memories has a different memory capacity than at least one other memory of the plurality of memories is provided. The method may include determining a smallest memory capacity of the plurality of memories. The method may also include allocating a node-interleaved memory using a portion of each memory equal to the smallest memory capacity. For each particular memory not fully allocated to the node-interleaved memory, each portion of each particular memory not allocated to the node-interleaved memory may be associated with a node local to the particular memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.