Parity error detecting circuit and method
US8122334B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 27, 2007 |
| Grant date | Feb 21, 2012 |
| Priority date | — |
| Expiry date | Dec 20, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0061
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A parity error detecting circuit includes a first operation unit, a second operation unit, and a shift register. The first operation unit receives a serial data signal and a first signal, performs a logic operation on the two received signals, and outputs the result of the logic operation as the first signal in response to a first clock signal. The shift register shifts the first signal in response to the first clock signal and outputs a second signal. The second operation unit receives the first signal and the second signal, performs a logic operation on the two received signals, and outputs the result of the logic operation in response to a second clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.